About the Role

We are seeking an experienced AMS (Analog Mixed-Signal) Layout Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 3nm technology node.

In this role, you will be responsible for the layout of advanced analog and mixed-signal circuits, ensuring performance, matching, and manufacturability for high-speed transceiver applications in cutting-edge process nodes.

Key Responsibilities

• Perform full-custom layout of high-speed SerDes design such as RX Front-ends, TX Drivers, PLLs, CDRs, bias circuits, ADCs/DACs.
• Handle layout of high-frequency components with emphasis on parasitic minimization, shielding, and routing symmetry.
• Floorplan and assemble top-level analog/mixed-signal and perform layout integration.
• Work closely with circuit designers to understand schematic intent, matching, symmetry, and parasitic sensitivity.
• Ensure high-quality layout practices to meet DRC, LVS, ERC, and EM/IR signoff in advanced FinFET processes (High-end process nodes).
• Perform layout-versus-schematic (LVS), design rule checks (DRC), and parasitic extraction (PEX) using industry-standard tools (Cadence Virtuoso XL, Calibre ...), .
• Support post-layout simulation by extracting and delivering clean parasitic netlists (RC).
• Collaborate with physical design and digital implementation teams on analog-digital boundary integration.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or related field.
• 7+ years of experience in custom analog or mixed-signal layout in deep-submicron or FinFET processes.
• Strong experience with:

o High-speed SerDes designs, PLLs, ADCs/DACs, power management units.

o Handling sensitive matching and noise isolation constraints (e.g., differential pair matching, guard rings).

o Tools like Virtuoso Layout Editor, Calibre, PVS, StarRC, Quantus, or similar.

• Strong understanding of semiconductor physics, CMOS fabrication processes, and advanced process nodes (e.g., 7nm and below).
• In-depth knowledge of layout techniques for minimizing parasitics, noise, and ensuring robust circuit operation.
• Experience with layout debugging and tapeout release process.

Pay and Benefits

• Competitive salary.
• Performance bonus each year.
• Long Term Incentive (LTI)
• Flexible working time.
• Health check each year.
• Insurance for engineer and family.
• Lunch Allowance.
• Company trips