Scope

As the Staff Engineer, Analog Layout at Ambiq, you will drive the physical implementation of key analog subsystems, including PMUs, clocking, and data converters, translating circuit architecture into silicon-ready layout that meets performance, area, matching, and reliability targets.

This role works closely with Analog Design and RTL/Physical Design teams to implement custom analog layouts that meet and exceed customer needs. Designs will be in leading-edge technologies, such as 22nm, 12nm, and beyond.

The successful candidate will be a highly motivated team player who, through collaboration with designers and layout peers, will help everyone succeed.

The person in this role will be well-rounded, having been through a number of design cycles. They will have layout-related experience across the full flow, from floorplanning and whiteboarding with designers, to detailed layout and parasitic extraction, to LVS/DRC closure and tape-out, through validation and production test support.

This role will be onsite, and the candidate will be expected to have a presence on site 5 days a week.

Responsibilities

• Partner with analog designers on chip-level and block-level floorplanning and layout strategy

• Drive layout architecture decisions to balance performance, matching, area, and reliability trade-offs

• Execute transistor-level analog IC layout, including critical matching, shielding, and parasitic-sensitive structures

• Lead layout for complex blocks and closely supervise or review layout work from other layout engineers

• Conduct layout design reviews and resolve action items generated as a result of these reviews

• Attend circuit design reviews to provide layout feasibility input and guidance to designers and other layout engineers

• Work with analog and digital designers to ensure layout meets circuit intent and interface requirements

• Own parasitic extraction, LVS, DRC, antenna, and fill closure for assigned blocks and top-level integration

• Support prototype chip bring-up and testing to help validate analog circuit blocks against layout-dependent effects

• Support development of manufacturing test plans where layout impacts testability (e.g., probe access, trim structures)

• Support Product Engineering to meet manufacturing/production needs related to layout and yield

• Support Applications Engineering on layout-related customer questions (e.g., matching, noise, reliability)