Role Summary We are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership — driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose.

Responsibilities — What You Will Own

• Chief of Staff to Head of Engineering
• Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs. • Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate. • Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes. • Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions. • Support org design, headcount planning, and hiring prioritization for engineering teams. • Maintain alignment across functions through clear messaging and communication, validate exitance and validation of processes • Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety. • Support the head of engineering with administrative and org related activities
• Lead ASIC Tape out Management (Silicon Programs)
• Status management — collect and track status across functions contributing to ASIC tapeouts. • Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence. • IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops. • Quality & documentation — monitor quality KPIs, ensure engineering documentation completeness. • Requirements tracking — ensure PRDs/features are captured, tracked, baselined. • Resource monitoring — track compute, hardware, storage consumption and thresholds. • Internal reporting — generate status reporting for Silicon Engineering leadership.
• Influence Without Authority
• Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy. • Create order in ambiguous spaces; shape scope where it is undefined.

Qualifications

• 10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies). • Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role. • Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs. • Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.). • Proven ability to organize complex workflows and drive consistent follow-through. • High EQ and organizational awareness; can navigate tension and align diverse viewpoints. • Exceptional written/verbal communication, structured thinking, and execution discipline. • Prior experience in leading RTL2GDSII chip design is a huge plus.

What Success Looks Like

• Engineering leadership spends more time on strategic and technical decisions, less on coordination. • Milestones hit with fewer escalations and clearer accountability. • Status, risks, and decisions are crisp — never ad hoc or late. • Teams feel supported, not policed — trust increases, friction decreases without compromising on accountability . • Ambiguity decreases over time as clarity and execution rhythm scale with the org.

Salary range is $216,000 to $300,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.