We’re looking for a Principal RTL Engineer to own pre-tapeout quality for digital SoC modules on our MCU platforms and drive architecture, microarchitecture, and RTL development for next-generation silicon.

In this role, you’ll develop Verilog/SystemVerilog RTL for complex IPs and SoCs, evaluate and integrate 3rd-party IP, partner closely with verification and FPGA teams on test planning and debug, collaborate with physical design to hit timing and power targets, and drive LINT, CDC, RDC, silicon bring-up, and validation quality.

This is a hands-on principal IC role for an engineer who has built and debugged complex SoCs, knows how to raise quality before tapeout, and wants direct impact on production silicon.

Responsibilities

• Own and be responsible for pre-tape out quality for digital SOC modules on the MCU
• Explore architecture and develop micro-architecture.
• RTL development for IPs and SOCs using Verilog
• 3rd party IP identification, selection, and integration
• Collaboration with verification and FPGA teams in test plan development and debug
• Collaborate with the Physical Design team to close the design on timing and power targets
• Assist in silicon bring-up and validation;
• Run tool for quality checks (LINT, CDC, and RDC) and fix/waive the issues

• Bachelor’s degree in Electronics Engineering, Electrical Engineering, Instrumentation & Control Engineering, or a related field, plus 20 years of experience.
• Possess deep and broad knowledge of current and emerging SOC design technologies.
• Have expert knowledge in designing, implementing, and troubleshooting IPs and SOC
• Demonstrate a deep understanding of customer needs and the competitive landscape.
• Ability to estimate the impact of and help plan and lead the implementations and have a positive impact on the entire output
• Can architect and guide programs across the full range of technical areas.