Additionalinformation

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

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Company Description

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Job Description

About the Role

Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own the FPGA-based platforms that emulate our mixed-signal power ASICs before silicon. Working shoulder to shoulder with our silicon RTL and DSP architects, you will bring their designs up on FPGA to validate real-time digital, mixed-signal, and power-control architectures pre-silicon — proving out control loops, catching RTL issues early, and de-risking tape-out.

These FPGA platforms are emulation vehicles, not production hardware. Success is measured by how faithfully and how fast they reproduce the target silicon: functional equivalence to the golden ASIC RTL, real-time (or near-real-time) performance for closed-loop power and DSP validation, and deep visibility for pre-silicon debug.

What You'll Do

• Partner closely with silicon RTL and DSP architects to bring ASIC designs up on FPGA — advising on FPGA-ability and turning architectural intent into a working, real-time emulation platform.
• Adapt ASIC RTL for FPGA emulation while preserving functional equivalence to the golden design — handling clock-gating conversion, memory/SRAM macro mapping, reset and initialization schemes, tri-state/bus conversion, and stubbing or modeling of analog/mixed-signal blocks.
• Map designs onto the FPGA fabric to fit and to hit emulation speed — steering resource inference (DSP/multiplier slices, block vs. distributed memory), clocking, and pipelining so the design achieves the real-time performance the validation requires.
• Build the real-time environment around the digital core: model or interface to the analog and power stages (ADC/DAC/PWM, gate drivers, plant/converter models), including hardware-in-the-loop with real or emulated power hardware where needed.
• Develop deep pre-silicon debug and visibility — logic analysis, long-run waveform capture, triggering, and assertions — and enable firmware/software co-development ahead of silicon.
• Define and continuously improve the emulation methodology, RTL/FPGA-ability guidelines, flows, and automation (TCL/Python).
• Provide technical leadership: mentor engineers, lead reviews, and drive emulation and tooling decisions across the silicon and systems teams.

Qualifications

Required Qualifications

• Extensive FPGA design and implementation experience (typically 10+ years), including a track record of FPGA prototyping or emulation of ASIC/SoC designs.
• Expert-level RTL design in SystemVerilog and/or VHDL, with deep familiarity working from ASIC-style RTL.
• Deep understanding of FPGA internal architecture and primitives — DSP/multiplier slices, block and distributed RAM, carry chains, and clocking — and a proven ability to map designs onto these resources to fit large ASIC RTL and reach real-time emulation performance (memory/SRAM macro mapping, DSP inference, clock-enable conversion, control-set and fanout management).
• Hands-on experience adapting ASIC RTL for FPGA: clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling.
• Strong command of the full FPGA implementation flow — synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) — on large Xilinx and/or Intel (Altera) devices, using Vivado and/or Quartus.
• Hardware bring-up and debug experience: in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug.
• Proficiency scripting for automation (TCL, Python).
• Demonstrated technical leadership — mentoring, reviews, and driving cross-team technical decisions.
• BS or MS in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).

Preferred Qualifications

• Real-time, hardware-in-the-loop emulation and modeling of analog/mixed-signal and power stages (ADC/DAC/PWM interfaces, plant/converter models).
• Understanding of digital power-conversion control and mixed-signal systems — converter topologies, control loops, PWM/PFM, and magnetics — to build faithful models and validate power-control architectures.
• FPGA DSP implementation and real-time emulation of DSP datapaths: FIR/IIR/CIC filters, interpolation/decimation, FFT, FEC, including high-throughput techniques such as folding/unfolding.
• Experience with commercial FPGA prototyping platforms such as Synopsys HAPS, Cadence Protium, or Siemens Veloce.
• Model-based design with Simulink and/or Xilinx System Generator.
• High-speed interface experience: JESD204B, PCIe, 1G/10G Ethernet, Aurora.
• ASIC design or tape-out exposure, including DFT/scan considerations in emulation.
• Ability to architect and build a custom in-house FPGA prototyping platform — board architecture, high-speed PCB design, signal integrity, and bring-up — a plus as we may develop our own hardware in the future.
• Embedded/microcontroller and firmware co-development experience (C/assembly); MATLAB, C/C++.

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