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Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

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We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

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Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

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Company Description

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Job Description

Renesas is seeking a Senior Staff Digital Design Verification Engineer to lead verification architecture, methodology and signoff for our Austin team's digitally controlled power-management ICs, which power datacenter, AI accelerator, enterprise computing and networking systems. These chips combine a multiphase digital control loop, telemetry, fault and alert management, PMBus, AVSBus and high-speed power-management bus interfaces, an embedded microcontroller running production firmware, and non-volatile configuration, all integrated with high-performance analog. This is a hands-on technical leadership role. You will own the verification strategy and tapeout signoff for a controller program, architect the UVM-based environment in which our next generation of controllers will be verified, lead the migration of a large, mature directed-random SystemVerilog environment and its regression suite onto that platform, and raise the technical level of the verification team through review and mentorship. You set direction and are accountable for the result, while still writing testbench code, debugging the hardest failures and making the call on what is and is not ready to ship

Responsibilities:

• Own the chip-level verification strategy, plan and signoff for a power-management controller program, from product requirements through tapeout, and present closure evidence and residual risk to engineering and program leadership.
• Architect the next-generation UVM verification environment for the controller family: the analog interface and real-number modeling strategy, register model integration with firmware-driven and non-volatile configuration, protocol agents for the power-management buses, reuse across derivatives, and a migration path that keeps the existing regression suite running throughout.
• Define and enforce verification methodology across the team: verification plan structure, coverage model and closure criteria, assertion and checker standards, coding guidelines and review practice.
• Lead technical reviews of verification plans, testbench architecture, checkers and coverage models written by other engineers, and mentor senior and junior engineers toward full ownership of their blocks.
• Decide where formal verification, gate-level simulation, FPGA or emulation add value beyond simulation, and drive their adoption.
• Own the verification infrastructure roadmap: regression dispatch on a compute grid, coverage merge and analytics, failure triage automation, and register and configuration generators, in Python, Perl and Tcl.
• Lead debug of the most difficult failures across RTL, testbench, firmware, analog models and specification, and turn root causes into methodology and checker improvements.
• Support silicon bring-up and validation, drive pre-silicon to silicon correlation, and run escape analysis that feeds back into the verification plan and methodology.
• Evaluate tools, verification IP and methodologies, and make build-versus-buy recommendations with cost and schedule justification.
• Estimate verification effort and staffing for new programs, and communicate status, risk and signoff evidence clearly to design, firmware, analog, validation, systems and program management.

Qualifications

Required:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or related field.
• 8 or more years of digital or mixed-signal design verification experience with a Bachelor's degree, or 6 or more years with a Master's degree, or equivalent directly applicable experience.
• Verification lead for at least one full-chip tapeout, owning the verification plan, coverage closure and signoff recommendation, preferably on a mixed-signal product.
• Architected and built a UVM environment from the ground up, including agents, score boards, register model, sequence library and coverage model, and sustained it across multiple projects or derivatives.
• Expert SystemVerilog and UVM: constrained-random stimulus, functional coverage modeling,
• SystemVerilog Assertions, and sound judgment about when directed, constrained-random or formal approaches fit the problem.
• Mixed-signal verification depth: defining real-number or behavioral model requirements for analog blocks, running and debugging analog/digital co-simulation, and signing off models against transistor-level or silicon behavior.
• Hardware/firmware co-verification experience on an embedded processor: able to read and write embedded C, reason about register maps and non-volatile configuration, and decide whether a failure belongs to firmware, RTL, the model or the specification.
• Demonstrated technical leadership: reviewing other engineers' verification plans and code, mentoring, and setting methodology that a team actually follows.
• Proficiency in Linux, Python and at least one of Perl or Tcl, with experience owning regression and coverage infrastructure on a grid scheduler such as LSF.
• Clear written and spoken communication of technical risk and signoff evidence to engineers and to program leadership.

Preferred:

• Verification of power-management ICs, voltage regulators, multiphase controllers or other digital control loops, including PWM generation, telemetry, fault and alert handling and power sequencing.
• Led a migration from a directed or module-based testbench to UVM on a live program without disrupting ongoing regressions.
• UVM register model integration with firmware-driven and non-volatile configuration, including generated register files.
• Expertise with PMBus, AVSBus, high-speed power-management bus protocols, I2C or SPI, and experience specifying or evaluating verification IP for them.
• Formal verification beyond connectivity checking: property checking, X-propagation, clock-domain crossing or reset verification with JasperGold or equivalent.
• Cadence Xcelium, SimVision, Verdi, vManager and JasperGold, and mixed-mode simulation with Spectre AMS or equivalent.
• Gate-level simulation, FPGA or emulation-based verification, silicon bring-up, and pre-silicon to silicon correlation and escape analysis.
• Experience estimating, staffing and scheduling verification for a chip program.

What You Bring • Technical judgment: knowing which verification approach fits a problem, and knowing when something is actually done. • Ownership of outcomes at the program level, not only of your own blocks. • The ability to set direction and build agreement across design, firmware, analog, systems and program management without relying on formal authority. • A commitment to developing other engineers and leaving the team stronger than you found it. • A practical approach to methodology change: improving how the team verifies without putting current programs at risk.

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