We are seeking a highly skilled Senior Physical Design Engineer to work on the implementation of complex digital blocks. In this role, you will leverage your expertise in advanced process nodes (3nm) to drive timing closure, power integrity, and physical verification for high-performance ASICs. Beyond standard digital flows, you will have the unique opportunity to work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trail blaze problems that are new to the photonics industry! If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team!

Responsibilities

• Implement digital blocks in advanced tech nodes from synthesis through physical verification, using industry standard tools and flows
• Drive fullchip STA signoff, review constraints, debug timing reports and implement ecos
• Drive power analysis and optimization while balancing area and performance trade-offs
• Drive full chip floor planning, IO placement and clock distribution
• Understand clock details and be able to customize clock implementation for functional and test clocks
• Debug and clean up DRC/LVS
• Functional and timing ECO implementation
• Work with EDA companies to resolve any tool issues
• Write TCL, Python, or Shell scripts to automate flow or customize existing flows

Qualifications

• Bachelor’s in Electrical Engineering or Computer Engineering
• 12+ years of industry experience working as a Physical Design Engineer
• Must have completed blocks or top level physical design for large ASICs or mixed signal chips that taped out
• Thorough knowledge of timing closure, LVS/DRC closure
• Experience in TCL and Python (or other scripting languages)
• Strong teamwork skills with the ability to collaborate with multiple functional teams across a variety of fields
• Ability to react to change and thrive in a fast paced environment

Preferred Qualifications

• Masters Electrical Engineering or Computer Engineering with 8 years of industry experience
• Hands-on experience with Cadence tools
• Tape-out experience 3nm designs
• Be willing to do manual layouts as well as willingness to learn and do silicon photonics layout
• EM/IR analysis using standard industry signoff tools